/*
 * (C) Copyright 2011-2015
 *
 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
 * Vladimir Skvortsov, Emcraft Systems, vskvortsov@emcraft.com
 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#include "clock.h"


/*
 * Set-up clock configuration.
 */
static void clock_setup(void)
{
}

/*
 * Initialize the reference clocks.
 */
void clock_init(void)
{
	unsigned int temp = 0; 
    
    /*set DCDC out 1.25v*/
    temp = DCDC_REG3;
    temp &= ~(DCDC_REG3_TRG_MASK);
    temp |= DCDC_REG3_TRG(0x12);
    DCDC_REG3 = temp; 
    
    // recover handshaking
    IOMUXC_GPR_GPR4  = 0x00000000;
    IOMUXC_GPR_GPR7  = 0x00000000;
    IOMUXC_GPR_GPR8  = 0x00000000;
    IOMUXC_GPR_GPR12 = 0x00000000;
    
    /*Congigurate ARM PLL1 as system clock*/
    CCM_ANALOG_PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK; //bypass PLL1
    
    /*Enalbe ARM PLL, POWRE ON. ARM PLL output 864Mhz */
    temp = CCM_ANALOG_PLL_ARM;
    temp &= ~CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; // ARM PLL power on
    temp &= ~CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
    temp |= CCM_ANALOG_PLL_ARM_ENABLE_MASK	//Enable the clock output
        | CCM_ANALOG_PLL_ARM_DIV_SELECT(100); //24*100/2 = 1.2Ghz
    CCM_ANALOG_PLL_ARM = temp;
    while(!(CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK));
    
    /*Set AHB_CLK_ROOT = 600Mhz, IPG_CLK_ROOT = 150Mhz,
    *     PERCLK_CLK_ROOT = 60Mhz.
    */
    /*ARM PLL output 1.2GHz
    * To set AHB_CLK_ROOT to 600Mhz, 1200/2/1 = 600Mhz
    * then should set CACRR[ARM_PODF] = 1, divide by 2
    * set CBCDR[AHB_PODF] = 0, divide by 1
    */
    CCM_CACRR = CCM_CACRR_ARM_PODF(1); //divide by 2
    
    temp = CCM_CBCDR;
    temp &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK; //derive clock from pre_periph_clk_sel
    temp &= ~CCM_CBCDR_IPG_PODF_MASK; 
    temp |= CCM_CBCDR_IPG_PODF(3);//divide by 4, IPG_CLK_ROOT = 600/4 = 150MHz
    temp &= ~CCM_CBCDR_AHB_PODF_MASK;
    temp |= CCM_CBCDR_AHB_PODF(0);	//divide by 1
    CCM_CBCDR = temp;
    
    /*Set PERCLK_CLK_ROOT to 48Mhz*/
    temp = CCM_CSCMR1;
    temp &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK; //derive clock from ipg_clk_root
    temp &= ~CCM_CSCMR1_PERCLK_PODF_MASK;
    temp |= CCM_CSCMR1_PERCLK_PODF(9); //divide by 10 , 600/10=60Mhz.
    CCM_CSCMR1 = temp;
    
    /*ARM PLL as clksource*/
    CCM_ANALOG_PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; 
    
    /*Select ARM PLL for pre_periph_clock */
    temp = CCM_CBCMR;
    temp &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
    temp |= CCM_CBCMR_PRE_PERIPH_CLK_SEL(3); 
    CCM_CBCMR = temp;
    /* enable eth clock */
    temp = CCM_ANALOG_PLL_ENET;
    temp &= ~CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; // ARM PLL power on
    temp |= ((1<<13)|(1<<19)|(1<<20));	//Enable the clock output
    CCM_ANALOG_PLL_ENET = temp;
    while(!(CCM_ANALOG_PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK));
	return;
}

/*
 * Return a clock value for the specified clock.
 * Note that we need this function in RAM because it will be used
 * during self-upgrade of U-boot into eNMV.
 * @param clck          id of the clock
 * @returns             frequency of the clock
 */
unsigned long clock_get(enum clock clck)
{
    // TODO: get clock
    switch (clck){
        case CLOCK_AHB:
            return 600000000;
        case CLOCK_IPG:
            return 150000000;
        case CLOCK_PER:
            return 60000000;
        case CLOCK_SYSTICK:
            return 600000000;
    }
    return 600000000;
}
